1. Field of the Invention
The invention relates generally to storage controllers and more specifically relates to methods and structure for using region lock structures to divert I/O requests to one of multiple I/O processing stacks of the storage controller.
2. Related Patents
This patent is related to the following commonly owned United States patents and/or patent applications (collectively referred to herein as the “Related Patents”):                U.S. patent application Ser. No. 12/760,415 entitled “APPARATUS AND METHODS FOR TREE MANAGEMENT ASSIST CIRCUIT IN A STORAGE SYSTEM” filed 14 Apr. 2010,        U.S. patent application Ser. No. 12/760,434 entitled “APPARATUS AND METHODS FOR REGION LOCK MANAGEMENT ASSIST CIRCUIT IN A STORAGE SYSTEM” filed 14 Apr. 2010, and        U.S. Pat. No. 7,529,902 entitled “METHODS AND SYSTEMS FOR LOCKING IN STORAGE CONTROLLERS” filed 19 Oct. 2005.        
All of which are hereby incorporated by reference.
3. Discussion of Related Art
A storage controller is a device adapted to receive I/O requests from one or more host systems and to process such received requests to store or retrieve data on storage devices coupled with the storage controller. For example, a RAID (Redundant Array of Independent Drives) storage controller manages one or more logical volumes that each comprises portions of one or more physical storage devices. The RAID controller maps logical block addresses of the logical volumes to corresponding physical blocks of the storage devices and provides redundancy and/or striping of the data for enhanced reliability and/or performance (in accordance with redundancy and striping policies of a particular RAID storage management technique defined for the logical volume).
It is common for high performance storage controllers to utilize a cache memory to enhance performance of the storage controller in processing I/O requests. For example, data written to a logical volume by a host system may be stored in the storage controller's cache memory such that subsequent read I/O requests may be satisfied by retrieving the requested data from the cache memory far more rapidly than by retrieving the requested data from the storage devices that comprise the logical volume. Some storage controllers may manage the cache memory as a “write-through” cache in which data is written to both the cache memory and to the storage devices. Some controllers may manage the cache memory in a “write-back” mode in which data is written to the cache memory and only posted/flushed to the storage devices at some later time (e.g., when the storage controller is less busy processing I/O requests). In the write-back mode, there could be data (referred to as “dirty data”) that resides in the cache memory but is not yet stored on the storage devices.
Some storage controllers (e.g., high-performance RAID storage controllers) provide for multiple processing pathways or stacks within the storage controller for processing I/O requests. For example, some storage controllers from LSI Corporation provides for a “fast path” processing circuit (e.g., a first processing pathway/stack) operable in conjunction with a firmware processing stack (e.g., a second/conventional processing pathway generally implemented as firmware instructions executed by a general or special purpose processor of the controller). The LSI Corporation fast path processing circuit works in conjunction with specialized drivers on the host systems to more rapidly process I/O requests formatted to allow the fast path circuit to rapidly process the request (e.g., the host system enhanced driver understands the RAID mapping and generates fast path requests to directly access the underlying physical storage devices thus allowing the fast path circuit to rapidly process the I/O request). The firmware processing pathway is adapted to process any type of I/O request received from any host system (e.g., for processing I/O requests regardless of its formatting as a fast path I/O request). The firmware stack handles more generalized processing using a general purpose processor executing instructions and providing full RAID mapping and management. Thus, though more flexible, the firmware processing stack processes I/O requests more slowly than does the fast path circuit.
In such storage controllers having multiple processing stacks (e.g., having a fast path circuit pathway and a firmware processing stack), some initial processing by the storage controller is necessary to determine which of the multiple processing stacks is appropriate for processing a particular I/O request. This initial processing can be a complex process depending on a number of factors. For example, if the storage controller utilizes its cache memory in a write-back mode, use of a fast path processing circuit may give rise to data integrity issues if there is dirty data presently in the cache memory of the storage controller that has not yet been flushed or posted to the storage devices. The fast path circuit may be optimally tuned in such a controller so that it is unaware of the contents of the cache memory and thus could write data to the storage devices that could later be overwritten if the dirty data is flushed. Or, the fast path circuit could read data from the storage devices that is not up to date because dirty data (more up to date data) is presently stored in the cache memory for the blocks accessed by the fast path circuit. Further, for example, if the firmware processing stack maintains a list of bad blocks to be avoided in storing or retrieving data from a logical volume or from particular storage devices, the fast path processing circuit may be unaware of the list of bad blocks and may again give rise to data integrity problems by attempting to access the potentially bad blocks. The fast path circuit may attempt to read or write data to such a bad block that only the firmware processing stack is aware may be bad. Other situations may arise where a firmware I/O request processing stack is presently engaged in certain optimizations such as coalescing smaller I/O requests to form full-stripe writes, optimization for streaming I/O requests, etc. These and other reasons may give rise to a preference for one I/O request processor of a storage controller over another despite an encoding of the request by the host to designate or prefer a particular processor.
Accounting for these various conditions in determining which of the multiple processing stacks is best suited for processing an I/O request can be a time-consuming, complex procedure. Thus, present techniques may simply disable the use of one of the multiple processing stacks (e.g., disable use of the fast path I/O processing circuit of LSI Corporation storage controllers) to avoid these and other potential problems if certain conditions may arise. For example, if any dirty data is presently stored in the write-back cache memory (regardless of whether a particular fast path I/O request may access that dirty data) or if any blocks are designated as “bad blocks” by the firmware processing stack (regardless of whether a particular fast path I/O request may access those bad blocks), the firmware processing stack disables the fast path processing circuit and chooses to process all I/O requests through its slower, but more generalized, processing pathway. In a conservative design approach, the LSI fast path I/O processing circuit may simply be disabled to avoid these and other problems arising by processing of an I/O request directed to the fast path circuit. Disabling use of the fast path I/O processing circuit may degrade performance of the storage controller.
Thus it is an ongoing challenge to effectively and efficiently determine which I/O processing stack is best suited for processing a particular I/O request and to divert a received I/O request to the preferred, selected I/O processing stack without risk of data integrity problems.